1. Field of the Invention
The present invention relates to a wirings structure of a semiconductor device, in particular, including wirings embedded in a vicinity of a surface of an insulating layer. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-6546 filed on Jan. 14, 2004, which is herein incorporated by reference.
2. Description of the Related Art
In a conventional method for forming copper wirings of the semiconductor device using damascene process, an insulating layer is formed on a semiconductor substrate and grooves for the wirings are formed in the insulating layer. Barrier layers and a copper wiring film are deposited in the grooves in sequence. The barrier layer prevents copper ions of the copper wiring film from diffusing into the insulating layer. After the above deposition, the copper wiring film and the barrier layers are smoothed by Chemical Mechanical Polishing method so as to be left only in the grooves of the insulating layer, and a covering film is formed on the copper wiring film and the insulating layer. When the covering film is made of insulating material, for example, silicon nitride, an adhesiveness between the covering film and the copper wiring film is low. Therefore, in an upper surface of the copper wiring film that is contact with the covering film, electro-migration easily occurs. As the result, the copper ions diffuse from the upper surface of the copper wiring film into the insulating film. That is, since copper hillocks grow through the interface between the covering film and the copper wiring film, leakage current can occur between adjacent copper wiring films.
To suppress the above leakage current, the wirings structure of the semiconductor device has been proposed as described in Document 1 (Japanese Patent Publication Laid-Open No. 2002-329780). In the wirings structure as described in the Document 1 (in particular, Page 15 and FIG. 20), a plurality of grooves for the wirings are formed in the insulating layer, and the barrier films and the copper wiring films are embedded in the grooves. After that, the surface of the insulating layer is located lower than the upper surfaces of the barrier film and the copper wiring film. A capping film is formed on the copper wiring film, the barrier film and the insulating film. The upper surface of the copper wiring film which is diffusion path of the copper ions is different from a boundary surface between the capping film and the insulating film in height. Thus, the leakage between the adjacent copper wiring films can be suppressed.
However, in the above-mentioned wirings structure of the semiconductor device as described in Document 1, reducing the thickness of the insulating film makes upper portions of the barrier film and the copper wiring film protruded from the surface of the insulating film. Since the area of the thinned insulating film accounts for a certain share of the entire area of wirings structure, the difference in level between the upper surface of the copper wiring film and the upper surface of the insulating film causes a larger step in the multi-level interconnects. Therefore, in the manufacturing method of the semiconductor device as described in Document 1, it is difficult to realize the exact microfabrication. In particular, in the multi-wiring structure, when the number of layers increases, it is difficult to realize the exact microfabrication as in the upper layer.
Therefore, it is necessary that the step between the copper wiring film and the insulating film is reduced and that the insulation performance is improved between the adjacent copper wiring films.